Development of Efficient On-Chip Networks for High-Performance Processors

High-performance computers have historically been one of the main drivers behind high-performance networks. A significant body of work into network toplogies, signalling techniques, routing, broadcast and reduction algorithms exists and continues to grow. However, to this day, modern high-performance computers, including the RIKEN“Next-Generation”supercomputer (NSC), are partitioned such that the high-performance interconnect is entirely distinct from the processors. In the case of the NSC, its processors contain at their heart a crossbar switch which has no interaction with the external network except through a dedicated I/O port. That is to say, it is not possible for individual processor cores to address each other through the network in a uniform manner; instead, cores in the same silicon processor “address” each other through the on-chip crossbar, while cores in different processor chips must traverse through the local crossbar, then through the interconnect, and finally through the destination chip’s crossbar. Currently, the fact that the interconnect fabrics of modern supercomputers do not reach into the processors themselves is not a major concern, since the number of cores in a processor is on the order of 10 or so.